1. Field of the Invention
This invention relates generally to electrically, erasable programmable read-only memory (EEPROM) cells implemented with a shallow trench isolation (STI) process. More particularly, it relates to an improved EEPROM cell having a field-edgeless tunnel window which is fabricated by a STI process so as to produce reliable endurance and data retention.
2. Description of the Prior Art
As is generally well-known, one type of isolation technology used very extensively in the past for isolating active devices on a high density semiconductor integrated circuit is referred to as "LOCOS" (isolation for local oxidation of silicon). However, as the active device geometries were reduced or shrunk down to deep sub-micron dimensions (&lt;0.25 .mu.m) in the integrated circuit process to achieve higher densities, the effectiveness of the LOCOS isolation technique was significantly degraded. As a consequence, there was developed a newer scalable isolation process referred to as "shallow trench isolation" (STI) in which trenches are etched adjacent active regions of the semiconductor substrate. Nevertheless, the STI technology was not without its own problems, such as adversely affecting the quality of the tunnel oxide at the STI corners thereby reducing the data retention capability of the EEPROM cell.
In fact, it has been determined that EEPROM cells implemented with standard logic STI process have a worse cell endurance/data retention characteristic than the EEPROM cells fabricated using the LOCOS isolation technique. This is caused by the non-rounded corners at the STI edges. One way of overcoming the problem of STI cell data retention in the EEPROM cell is achieved by increasing the liner thickness of the liner oxide layer to approximately 1,000 .ANG., as is described and illustrated in co-pending application Ser. No. 08/947,888 filed on Oct. 9, 1997, and entitled "Improving Data Retention of EEPROM Cell with Shallow Trench Isolation Using Thicker Liner Oxide." This application Ser. No. 08/947,888 is assigned to the same assignee as in the present invention. By increasing the liner oxide thickness, the isolation structure will not be degraded by the subsequent fabrication etching step which might cause leakage current from the side walls of the trenches.
However, this approach suffers from the disadvantage that it sometimes requires a relatively long period of development so as to modify the existing standard logic STI process in order to obtain the needed data retention characteristic in the EEPROM cell. Therefore, there is still a need for an improved EEPROM cell having a field-edgeless tunnel window without requiring modification to the STI process.